1. Field
Various embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a delay locked loop (DLL) circuit.
2. Description of the Related Art
In a system or circuit, a clock is used as a reference signal for adjusting operation timing, and helps to assure high-speed operation without errors. When an external clock is inputted to be used in the system or circuit, there may be clock skew caused by time delays in one of the internal circuits. A delayed locked loop (DLL) is used to correct time delays so the internal clocks are synchronized with the external clocks.
FIG. 1 is a diagram illustrating a conventional DLL circuit.
Referring to FIG. 1, the conventional DLL circuit includes a clock dividing unit 110, a delay line unit 120, a replica delay unit 130, a phase comparison unit 140, and a delay control unit 150.
The clock dividing unit 110 receives external differential clocks CLK and CLKB, and generates a first internal lock ICLK and a second internal clock QCLK by dividing the received external differential clocks CLK and CLKB. The external clock CLKB is complementary to the external clock CLK, and thus the second internal clock QCLK has a phase difference of 180 degrees from the first internal clock ICLK.
The delay line unit 120 delays the first and second internal clocks ICLK and QCLK according to a delay control signal CTRL, and outputs the delayed signals as first and second delay locked clocks DLLCLKI and DLLCLKQ.
The replica delay unit 130 reflects an actual delay of a clock path and a data path into the first delay locked clock DLLCLKI outputted from the delay line unit 120, to output a feedback clock FBCLK. The feedback clock FBCLK is obtained by adding a delay time of the delay line unit 120 and a delay time of the replica delay unit 130 to the first internal clock ICLK.
The phase comparison unit 140 compares a phase of the external clock CLK to a phase of the feedback clock FBCLK to output a comparison result UP/DN.
The delay control unit 150 generates the delay control signal CTRL based on the comparison result UP/DN outputted from the phase comparison unit 140.
While repeating such a series of loop operations, the DLL circuit continuously compares the first internal clock ICLK to the feedback clock FBCLK, and outputs the desired first delay locked clock DLLCLKI when the two clocks have a minimum jitter (i.e., when the first delay locked clock DLLCLKI is locked). The delay control unit 150 performs an update operation at each predetermined period after locking. During the update operation, jitter may occur in the first and second delay locked clocks DLLCLKI and DLLCLKQ, which were previously locked, due to noise or the like. Thus, to compensate for the jitter, the locking process is repetitively performed. The first and second delay locked clocks DLLCLKI and DLLCLKQ, which are eventually outputted, may be generated by delaying the external clock CLK. As such, the first and second delay locked clocks DLLCLKI and DLLCLKQ, which are eventually outputted, may be used during a data output operation for outputting data. The first internal clock ICLK is used during an update operation of the DLL circuit. The second internal clock QCLK is not used during the update operation of the DLL circuit, but the second delay locked clock DLLCLKQ obtained by using the second internal clock QCLK is used during a data output operation.
The conventional DLL circuit continuously generates the first and second delay locked clocks DLLCLKI and DLLCLKQ by repeating the locking operation even when a delay locked clock is not used. Thus, the conventional DLL circuit causes unnecessary current consumption.